The power consumption of CMOS-based cryptographic circuits depends strongly on the data being processed by the circuits. A correlation between the power consumed by the circuit and the data being processed by the circuit can be exploited to obtain the stored critical information by a malicious attacker utilizing a side-channel attack (SCAs). Differential power analysis (DPA) attacks are one of the most widely studied SCAs that exploit the switching activities within the cryptographic circuits while the circuits process different input data. Recently, leakage power analysis (LPA) attacks have been disclosed that may be utilized for obtaining the critical information by analyzing the correlation between the input data and leakage power dissipation of the cryptographic circuit. LPA attacks exploit the fact that the leakage current signature of NMOS and PMOS transistors is different than dynamic power, where the amplitude of leakage power is orders of magnitude smaller than the amplitude of dynamic power consumption. To perform a successful LPA attack, the attacker must mitigate the measurement noise that can make the analysis quite difficult due to the small signal-to-noise ratio (SNR) of the monitored leakage power. An effective technique to mitigate the measurement noise is to lower the operating frequency of the cryptographic circuit.
Since the leakage mechanisms in DPA and LPA attacks are quite different, DPA-resistant cryptographic circuits may still be vulnerable against LPA attacks. Therefore, there is a strong need for effective countermeasures against LPA attacks.